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| EtronTech Features * Fast clock rate: 300/275/250/200/166 MHz * Differential Clock CK & CK# input * 4 Bi-directional DQS. Data transactions on both edges of DQS (1DQS / Byte) * DLL aligns DQ and DQS transitions * Edge aligned data & DQS output * Center aligned data & DQS input * 4 banks operation * Programmable mode and extended mode registers - CAS# Latency: 3, 4 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleave * Full page burst length for sequential type only * Start address of full page burst should be even * All inputs except DQ's & DM are at the positive edge of the system clock * No Write-Interrupted by Read function * 4 individual DM control for write masking only * Auto Refresh and Self Refresh * 4096 refresh cycles / 32ms * Power supplies : VDD = 2.5V 5% VDDQ = 2.5V 5% * Interface : SSTL_2 I/O compatible * Standard 144-ball FBGA package * Pb-free package is available EM6AA320-XXMS 8M x 32 DDR SDRAM (Rev 0.7 May/2006) Overview The EM6AA320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK#. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command. The EM6AA320 provides programmable Read or Write burst lengths of 2, 4, 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6AA320 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. Ordering Information Part Number (*) EM6AA320BI-3.3MS (*) EM6AA320BI-3.6MS (*) EM6AA320BI-4MS/4MSG (*) EM6AA320BI-5MS/5MSG (*) EM6AA320BI-6MS/6MSG Note (*) : S indicates stacked die package G indicates Pb-free package Frequency 300MHz 275MHz 250MHz 200MHz 166MHz Power Supply VDD 2.5V VDDQ 2.5V Package FBGA FBGA FBGA FBGA FBGA EtronTech 1 A DQS0 2 DM0 3 VSSQ 4 DQ3 8Mx32 DDR SDRAM EM6AA320-XXMS 9 DQ28 10 VSSQ 11 DM3 12 DQS3 Pin Assignment (FBGA 144Ball Top View) 5 DQ2 6 DQ0 7 DQ31 8 DQ29 B DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 C DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 D DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 E DQ17 DQ16 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ15 DQ14 F DQ19 DQ18 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ13 DQ12 G DQS2 DM2 NC VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ NC DM1 DQS1 H DQ21 DQ20 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ11 DQ10 J DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 K CAS# WE# VDD VSS A10 VDD VDD NC VSS VDD NC NC L RAS# NC NC BA1 A2 A11 A9 A5 NC CK CK# NC M CS# NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF Pin Assignment by Name (FBGA 144Ball) Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location A0 M4 DQ6 C1 DQ24 D12 CK L10 VDDQ B6 VSS E5 VSS J7 VSSQ G4 A1 M5 DQ7 D1 DQ25 C12 CK# L11 VDDQ B7 VSS E6 VSS J8 VSSQ G9 A2 L5 DQ8 J12 DQ26 C11 CKE M11 VDDQ B9 VSS E7 VSS K4 VSSQ H4 A3 M6 DQ9 J11 DQ27 B12 CS# M1 VDDQ B11 VSS E8 VSS K9 VSSQ H9 A4 M7 DQ10 H12 DQ28 A9 RAS# L1 VDDQ D2 VSS F5 VSSQ A3 VSSQ J4 A5 L8 DQ11 H11 DQ29 A8 CAS# K1 VDDQ D11 VSS F6 VSSQ A10 VSSQ J9 A6 M8 DQ12 F12 DQ30 B8 WE# K2 VDDQ E3 VSS F7 VSSQ C3 NC B3 A7 M9 DQ13 F11 DQ31 A7 VREF M12 VDDQ E10 VSS F8 VSSQ C4 NC B10 A8/AP M10 DQ14 E12 DQS0 A1 VDD C6 VDDQ F3 VSS G5 VSSQ C5 NC G3 A9 L7 DQ15 E11 DQS1 G12 VDD C7 VDDQ F10 VSS G6 VSSQ C8 NC G10 A10 K5 DQ16 E2 DQS2 G1 VDD D3 VDDQ H3 VSS G7 VSSQ C9 NC K8 A11 L6 DQ17 E1 DQS3 A12 VDD D10 VDDQ H10 VSS G8 VSSQ C10 NC K11 DQ0 A6 DQ18 F2 DM0 A2 VDD K3 VDDQ J3 VSS H5 VSSQ D5 NC K12 DQ1 B5 DQ19 F1 DM1 G11 VDD K6 VDDQ J10 VSS H6 VSSQ D8 NC L2 DQ2 A5 DQ20 H2 DM2 G2 VDD K7 VSS D4 VSS H7 VSSQ E4 NC L3 DQ3 A4 DQ21 H1 DM3 A11 VDD K10 VSS D6 VSS H8 VSSQ E9 NC L9 DQ4 B1 DQ22 J1 BA0 M3 VDDQ B2 VSS D7 VSS J5 VSSQ F4 NC L12 DQ5 C2 DQ23 J2 BA1 L4 VDDQ B4 VSS D9 VSS J6 VSSQ F9 NC M2 2 Rev 0.7 May. 2006 EtronTech Block Diagram 8Mx32 DDR SDRAM EM6AA320-XXMS Column Decoder De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #0) Sense Amplifier CK CK# CKE CS# RAS# CAS# WE# DLL CLOCK BUFFER CONTROL SIGNAL GENERATOR Sense Amplifier COMMAND DECODER MODE REGISTER De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #1) Column Decoder COLUMN COUNTER A8/A P Column Decoder De co de r Ro w A0 A 10 A 11 B A0 B A1 ADDRESS BUFFER 4096 X 512 X 32 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUNTER DQS0~3 DATA STR OBE BUFFER DQ0 DQ31 Sense Amplifier DQ BUFFER De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #3) Column Decoder DM 0~3 3 Rev 0.7 May. 2006 EtronTech Pin Descriptions Symbol CK, CK# Type Input 8Mx32 DDR SDRAM EM6AA320-XXMS Table 1. Pin Details of EM6AA320 Description Differential Clock: CK, CK# are driven by the system clock. All SDRAM input commands are sampled on the positive edge of CK. Both CK and CK# increment the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. They also define which Mode Register or Extended Mode Register is loaded during a Mode Register Set command. Address Inputs: A0-A11 are sampled during the Bank Activate command (row address A0-A11) and Read/Write command (column address A0-A7, and A9 with A8 defining Auto Precharge) to select one location out of the memory array in the respective bank. During a Precharge command, A8 is sampled to determine if all banks are to be precharged (A8 = HIGH). The address inputs also provide the opcode during a Mode Register Set or Extended Mode Register Set command. Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is started by asserting CAS# "LOW" Then, the Read or Write command is selected by asserting WE# "HIGH " or "LOW". Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: The DQSx signals are mapped to the following data bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to DQ24-DQ31. Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0. Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive edges of CK and CK#. The I/Os are byte-maskable during Writes. Power Supply: Power for the input buffers and core logic. CKE Input BA0, BA1 Input A0-A11 Input CS# Input RAS# Input CAS# Input WE# Input DQS0-DQS3 Input / Output Input DM0 - DM3 DQ0 - DQ31 VDD Input / Output Supply 4 Rev 0.7 May. 2006 EtronTech VSS Supply 8Mx32 DDR SDRAM EM6AA320-XXMS Ground: Ground for the input buffers and core logic. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. VDDQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VSSQ Supply Reference Voltage for Inputs: +0.5 x VDDQ VREF NC No Connect: These pins should be left unconnected. Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any applications using the single ended clocking, apply VREF to CK# pin. Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended Mode Register Set No-Operation Device Deselect Burst Stop AutoRefresh SelfRefresh Entry SelfRefresh Exit State CKEn-1 CKEn DM BA1 BA0 (3) Idle H X X V V Any H X X V V Any H X X X X Active(3) H X V V V (3) H X V V V Active (3) Active H X X V V Active(3) H X X V V Idle H X X L L Idle H X X L H Any H X X X X Any H X X X X Active(4) H X X X X Idle H H X X X Idle H L X X X Idle L H X X X (Self Refresh) H L X X X A8 A11-A9, A7-0 CS# RAS# CAS# WE# Row Address L L H H L X L L H L H X L L H L L L H L L Column H L H L L Address L A0~A7, A9 L H L H H L H L H L L L L OP code L L L L X X L H H H X X H X X X X X L H H L X X L L L H X X L L L H H X X X X X L H H H H X X X X X L H H H H X X X X X L H H H X X X X X X X X X X X X Power Down Mode Entry Idle/Active(5) Power Down Mode Exit Any L H X X X (Power Down) Active H X L X X Data Write/Output Enable Active H X H X X Data Mask/Output Disable Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA0, BA1signals. 4. Read burst stop with BST command for all burst types. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 5 Rev 0.7 May. 2006 EtronTech Mode Register Set (MRS) 8Mx32 DDR SDRAM EM6AA320-XXMS The mode register is divided into various fields depending on functionality. Burst Length Field (A2, A1, A0) * This field specifies the data length of column access and selects the Burst Length. Addressing Mode Select Field (A3) * The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode. CAS# Latency Field (A6, A5, A4) * This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. CAS# Latency X tCK tCAC(min) Test Mode field :A7; DLL Reset Mode field : A8 * These two bits must be programmed to "00" in normal operation. ( BA0, BA1) * Mode Resistor Bitmap BA1 0 BA0 A11 A10 A9 Mode RFU must be set to "0" BA0 0 1 Register Mode MRS EMRS A8 DLL A8 0 1 0 A7 TM A7 0 0 1 A6 A5 A4 CAS Latency A3 BT A3 0 1 A2 A1 A0 Burst Lenght A6 0 0 1 A5 1 1 0 A4 CAS Latency 0 Reserved 1 3 clocks 0 4 clocks All other Reserved Burst Definition, Addressing Sequence of Sequential and Interleave Mode Burst Length 2 4 Start Address A2 A1 A0 X X 0 X X 1 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 8 Mode Normal Reset DLL Test Mode Type Sequential Interleave A2 0 0 0 1 A1 0 1 1 1 A0 Burst Length 1 2 0 4 1 8 1 Full Page (Sequential) All other Reserved 6 Rev 0.7 May. 2006 EtronTech 8Mx32 DDR SDRAM EM6AA320-XXMS Extended Mode Register Set (EMRS) The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and WE#. The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS#, RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. Extended Mode Resistor Bitmap BA1 0 BA0 1 A11 A10 A9 A8 RFU must be set to "0" A7 A6 DS1 A5 A4 A3 A2 RFU must be set to "0" A1 DS0 A0 DLL BA0 Mode 0 MRS 1 EMRS A6 0 0 1 1 A1 Drive Strength Strength Comment 0 Full 100% 1 SSTL-2 weak 60% 0 RFU RFU Do not use 1 Matched impedance 30% Output driver matches impedance A0 DLL 0 Enable 1 Disable Power up Sequence Power up must be performed in the following sequence. 1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE "LOW". 2) Start clock and maintain stable condition for minimum 200us. 3) Issue a "NOP" command and keep CKE "HIGH" 4) Issue a "Precharge All" command. 5) Issue EMRS - enable DLL. 6) Issue MRS - reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS - with A8 to low to initialize the mode register. 7 Rev 0.7 May. 2006 EtronTech Absolute Maximum Rating Symbol VIN, VOUT VDD, VDDQ TA TSTG TSOLDER PD IOUT Item 8Mx32 DDR SDRAM EM6AA320-XXMS Unit Note Rating Non Pb-free package Pb-free package Input, Output Voltage Power Supply Voltage Ambient Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current - 0.3 ~ VDDQ+0.3 -0.3 ~ 3.6 0~70 - 55~150 240 260 2.0 50 V V C C C W mA Recommended D.C. Operating Conditions (SSTL_2 In/Out, TA = 0 ~ 70 C) Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC) VOH VOL IIL IOL Note : Parameter Min. Power Supply Voltage 2.375 Power Supply Voltage(for I/O ) 2.375 Input Reference Voltage 0.49 x VDDQ Termination Voltage VREF - 0.04 Input High Voltage VREF + 0.15 Input Low Voltage Vssq - 0.3 Output High Voltage Vtt + 0.76 Output Low Voltage Input Leakage Current Output Leakage Current -5 -5 Typ. 2.5 2.5 VREF - Max. Unit 2.625 V 2.625 V 0.51 x VDDQ V VREF + 0.04 V VDDQ + 0.3 V VREF- 0.15 V V Vtt- 0.76 5 5 V uA uA Note 1 1 IOH = -15.2 mA IOL = +15.2 mA 1. Under all conditions VDDQ must be less than or equal to VDD. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 C) Parameter Input Capacitance (A0~A11, BA0, BA1) Input Capacitance (CK, CK#, CKE, CS#, RAS#, CAS#, WE#) DQ & DQS input/output capacitance DM0~DM3 input/output capacitance Note: These parameters are periodically sampled and are not 100% tested. Symbol CIN1 CIN2 COUT CIN3 Min. 8 6 6 6 Max. 10 10 9 9 Unit pF pF pF pF 8 Rev 0.7 May. 2006 EtronTech D.C. Characteristics (VDD =2.5 5%, TA = 0~70 C) 8Mx32 DDR SDRAM EM6AA320-XXMS 3.6 4 Max 350 5 6 Parameter & Test Condition OPERATING CURRENT : One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-ReadPrecharge; BL=4; CL=4; tRCDRD=4*tCK; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE=LOW IDLE STANDLY CURRENT : CKE = HIGH; CS#=HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS#=HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Sell Refresh Mode ; CKE<=0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputschang only during Active, READ , or WRITE command Symbol 3.3 Unit IDD0 500 460 310 280 mA IDD1 600 540 480 440 400 mA IDD2P 120 120 100 80 80 mA IDD2N 210 200 175 170 170 mA IDD3P 120 120 100 80 80 mA IDD3N 300 280 260 240 240 mA IDD4R 640 610 580 550 520 mA IDD4W 550 525 500 480 460 mA IDD5 IDD6 750 8 720 8 650 5 610 5 580 5 mA mA IDD7 1100 1050 1000 950 900 mA Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. Power-up sequence is described in previous page. 9 Rev 0.7 May. 2006 EtronTech 8Mx32 DDR SDRAM EM6AA320-XXMS Unit uF uF Decoupling Capacitance Guide Line Symbol Parameter CDC1 Decouping Capacitance between VDD and VSS CDC2 Decouping Capacitance between VDDQ and VSSQ Value 0.1+0.01 0.1+0.01 AC Input Operating Conditions (VDD = 2.5 5%, TA = 0~70 C) Symbol VIH VIL VID VIX Parameter Input High Voltage; DQ Input Low Voltage; DQ Clock Input Differential Voltage; Ck & CK# Clock Input Crossing Point Voltage; Ck & CK# Min VREF+0.4 0.8 0.5xVDDQ-0.2 Max VREF-0.4 VDDQ+0.6 0.5xVDDQ+0.2 Unit V V V V Note AC Operating Test Conditions (VDD = 2.5 5%, TA = 0~70 C) Reference Level of Output Signals (VRFE) CK & CK# signal maximum peak swing Output Load Input Signal Levels Input Signals Slew Rate Input timing measurement reference level Output timing measurement reference level Reference Level of Input Signals 0.5 x VDDQ 1.5V See Figure. A Test Load VREF+0.4 V / VREF-0.4 V 1 V/ns VREF VTT 0.5 x VDDQ Figure A. Test Load VTT=0.5 x VDDQ 50 DQ,DQS Z0=50 W 30pF VREF=0.5 x VDDQ 10 Rev 0.7 May. 2006 EtronTech (VDD = 2.5 5%, TA = 0~70 C) Symbol Parameter 8Mx32 DDR SDRAM EM6AA320-XXMS 5 Max Min Max Min 6 Max Unit Electrical Characteristics and Recommended A.C. Operating Conditions Min 3.3 Max Min 3.6 Max 4 Min tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD twR tCDLR tCCD tMRD tDAL tXSA tPDEX tREF Clock cycle time Clock high level width Clock low level width CL = 3 CL = 4 3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 0.35 tCLMIN or tCHMIN 10 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 - 3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLMIN or tCHMIN 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - 4 4 0.45 0.45 -0.7 -0.7 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.45 0.45 tCLMIN or tCHMIN 10 10 0.55 0.55 0.7 0.7 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - 5 5 0.45 0.45 -0.7 -0.7 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 1.0 1.0 0.5 0.5 tCLMIN or tCHMIN 10 10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.15 0.6 0.6 0.6 - 6 0.45 0.45 -0.7 -0.7 0.9 0.4 0.75 0 0.25 0.4 0.35 0.35 1.0 1.0 0.45 0.45 tCLMIN or tCHMIN 12 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.25 0.6 - ns tCK tCK ns ns ns tCK tCK tCK ns ns tCK tCK tCK ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us DQS-out access time from CK,CK# Output access time from CK,CK# DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS write postamble DQS in high level pulse width DQS in low level pulse width Address and Control input setup time Address and Control input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS Clock half period Output DQS valid window Row cycle time Refresh row cycle time Row active time RAS# to CAS# Delay in Read RAS# to CAS# Delay in Write Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. Address to Col. Address delay Mode register set cycle time Auto precharge write recovery + Precharge Self refresh exit to read command delay tHP 0.35 17 19 12 6 4 5 3 3 2 1 1 9 200 tIS + 2tCK 100K - tHP 0.4 16 18 11 5 3 3 3 3 2 1 1 9 200 tIS + 2tCK 100K 7.8 tHP 0.45 15 17 10 5 3 3 3 3 2 1 2 8 200 tIS + 2tCK - tHP 0.5 12 14 8 4 2 4 2 2 2 1 2 6 200 tIS + 2tCK - THP 0.55 10 - 100K - 100K 7.8 12 7 3 2 4 2 2 2 1 2 6 200 tIS + 2tCK 100K 7.8 Power down exit time Refresh interval time - 7.8 - 7.8 11 Rev 0.7 May. 2006 EtronTech Timing Waveforms 0 CK# CK tIS tIH RD tCK tCH 1 tCL tHP 8Mx32 DDR SDRAM EM6AA320-XXMS Figure 1. AC Parameters for Read Timimg (Burst Length = 4) 2 tHP 3 4 5 6 7 8 CMD A0-11, BA0-1 tIS tIH Valid CAS Latency = 5 "Preamble" tRPRE tAC tDQSCK "Postmble" tRPST tQHS DQ0 tDQSQ CAS Latency = 4 DQ1 DQ2 DQ3 tQH "Postmble" DQS DQ DQS "Preamble" DQ CAS Latency = 3 DQS DQ0 DQ1 DQ2 DQ3 "Preamble" "Postmble" DQ DQ0 DQ1 DQ2 DQ3 Figure 2. AC Parameters for Write Timing (Burst Length=4) CK# CK CMD A0-11, BA0-1 WR WR WR 0 1 2 3 4 5 6 7 8 Valid "Preamble" "Postmble" tWPST Valid Valid "Postmble" "Preamble" tDQSS tDS tDH tDS Input Data Masked tDH tWPST DQS tWPRES tWPREH tDQSS DM tDS DQ DQ0 DQ1 DQ2 tDH DQ3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 12 Rev 0.7 May. 2006 EtronTech CK tRCDRD tRAS tRC CMD ACT RD PRE 8Mx32 DDR SDRAM EM6AA320-XXMS Figure 3. Bank Activate Read or Write Command Timing tRCDWR tRP tRRD ACT ACT WR tRAS tRC PRE ACT tRP ROW ADR Active A0-11 RA ROW ADR BA0-1 BA Bank ADR CA Column ADR BA Percharge RA RA CA RA BA BA BA BA BA BA Figure 4. Burst Stop for Read (CAS Letancy = 5, Burst Length = 4) CK# CK CMD RD BST Burst Stop for CAS Latency = 5 A0-11, BA0-1 DQS Valid After 1 x CK Command can be active 1x CK CMD 0 1 2 3 4 5 6 7 8 DQ DQ0 DQ1 Figure 5. Read with Auto Precharge (CAS Letancy = 5, Burst Length = 4) CK# CK Read with Auto Precharge CMD RDA CAS Latency = 5 A0-11, BA0-1 DQS Begin of Auto Precharge DQ DQ0 DQ1 DQ2 DQ3 Valid tRP Valid Bank can be Active after Auto Precharge ACT 0 1 2 3 4 5 6 13 Rev 0.7 May. 2006 EtronTech CK# CK 0 1 2 8Mx32 DDR SDRAM EM6AA320-XXMS 6 Figure 6. Write with Auto Precharge (Burst Length = 4) 3 4 5 Write with Auto Precharge CMD WRA Bank can be Active after Auto Precharge ACT A0-11, BA0-1 DQS Valid tWR Begin of Auto Precharge tRP Valid DQ DQ0 DQ1 DQ2 DQ3 Figure 7. Read Burst Interrupt by Read (CAS Letancy = 5, Burst Length = 4) CK# CK tCCD CMD RDa RDb 0 1 2 3 4 5 6 7 8 A0-11, BA0-1 DQS Valid Valid DQ Da0 Da1 Db0 Db1 Db2 Db3 Figure 8. Write Interrupted by Write (Burst Length = 4) CK# CK tCCD CMD WRa WRb 0 1 2 3 4 A0-11, BA0-1 DQS Valid Valid DQ Da0 Da1 Db0 Db1 Db2 Db3 Figure 9. Auto Refresh Timimg CK tRP CMD PRE Precharge AFRF Auto Refresh E it tRFC CMD 14 Rev 0.7 May. 2006 EtronTech Figure 10. Self Refresh Timimg CK 200xCK tSREX CMD SREF SREX NOP 8Mx32 DDR SDRAM EM6AA320-XXMS CMD CKE Self Refresh Entry Self Refresh Exit After 200 x CK, Command can be active Figure 11. Precharge Command CK tRAS tRC CMD ACT PRE ACT tRP A0-11 RA RA BA0-1 BA BA BA Figure 12. Power Up Sequence CK 200uS CMD NOP Power Up wait 200uS NOP PREA Precharge All tRP EMRS EMRS set tMRD MRS MRS set Reset DLL with A8=H 200xCK PREA Precharge All tRP AREF AREF 2 or more Auto Refresh tRFC MRS MRS set with A8=L Figure 13. Mode Register Set Timing CK 1xCK MRS MRS set tRP CMD PREA Precharge All tMRD CMD After 1 x CK, Command can be active Figure 14. Power Down Mode CK CMD PRE NOP NOP NOP tPDEX CMD CKE Power Down Mode Entry Power Down Mode Exit 15 Rev 0.7 May. 2006 EtronTech TOP VIEW 8Mx32 DDR SDRAM EM6AA320-XXMS BOTTOM VIEW 0.08 S 0.15 S C C A PIN A1 CORNER B PIN A1 CORNER 0.40~0.50 (144X) 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1 123456 L L -A1.60 0.80 8.80 0.20 C -B0.15 (4x) C \\ Ball pitch : 0.80 0.15 C -CSEATING PLANE Ball Diameter : 0.45 16 Rev 0.7 May. 2006 |
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